1. Field of the Invention
The present invention relates to a power supply control circuit, especially to a power supply control circuit which possesses an output transistor for controlling power supply to a load.
2. Description of Related Art
A power supply control circuit is known as a circuit which controls electric power supplied from a power source to a load. As one of the application areas, the power supply control circuit is used to drive an actuator and a lamp of an automobile.
The power supply control circuit comprises an output transistor serving as a switch which switches whether or not to supply electric power from a power source to a load. For example, an N-channel MOS transistor is used as an output transistor for a high-side switch. When driving the output transistor into an on state, it is necessary to make an on-resistance small enough by applying voltage higher than the power supply voltage to a gate of the output transistor. On the other hand, when driving the output transistor into an off state, it is necessary to discharge a charge stored at the gate thereof. However, in order to suppress a noise at the time of switching, severe restrictions are provided on a turn-off time and a slew rate.
FIG. 7 illustrates a circuit diagram of a semiconductor output circuit (a power supply control circuit) 100 disclosed by Japanese Patent Laid-open No. 2005-130245 and its counterpart U.S. Pat. No. 7,088,126 B2. As illustrated in FIG. 7, the power supply control circuit 100 comprises a gate driving circuit 131, an output transistor 132, a discharge circuit 133, a voltage detector 134, and a discharge circuit 135. The circuit configuration of the power supply control circuit 100 is explained in detail in the description of Japanese Patent Laid-open No. 2005-130245 and U.S. Pat. No. 7,088,126 B2; therefore, the explanation thereof is omitted here. FIG. 8 is a timing chart for explaining operation of the power supply control circuit 100 illustrated in FIG. 7. In FIG. 8, the vertical axis indicates voltage and current and the horizontal axis indicates time.
With reference to FIGS. 7 and 8, operation of the power supply control circuit 100 is explained. First, at time t1, an input signal “in” and a control signal “a” shift from a high level (for example, a power supply voltage Vcc) to a low level (for example, a ground voltage GND). Concurrently, a control signal “b” shifts from a low level to a voltage higher than the power supply voltage Vcc (for example, Vcc+10V). At time t2, a gate voltage G of the output transistor 132 shifts from a low level to a voltage higher than the power supply voltage Vcc (for example, Vcc+10 V). Thereby, the output transistor 132 is brought to an on state. Accordingly, the power supply control circuit 100 supplies electric power from the power source to an output terminal To. At this time, an output voltage Vo of the output terminal To is raised to substantially the same voltage level as the power supply voltage Vcc. This output voltage Vo is supplied to a load (not shown) of the next stage. A charge corresponding to the output voltage Vo is charged in a capacitor 136 via a parasitic diode of an NMOS transistor 138. Since a voltage of the control signal “c” is set to the same voltage level as the output voltage Vo, an NMOS transistor 137 is brought to an off state.
At time t3, the input signal “in” and the control signal “a” shift from a low level to a high level (the power supply voltage Vcc). Concurrently, in the gate driving circuit 131, the terminal which outputs the control signal “b” becomes in a high-impedance state. At this time, a depletion-type NMOS transistor 139 is brought to an on state. Therefore, a gate charge of the output transistor 132 is slowly discharged via a current limiting element 140 and the NMOS transistor 139.
Furthermore, at time t3, a voltage of the control signal “c” becomes a voltage level given by superposing the output voltage Vo to the voltage of the control signal “a.” Therefore, the NMOS transistor 137 is brought to an on state. Accordingly, the gate charge of the output transistor 132 is discharged at high speed via the NMOS transistor 137.
At time t4 after a delay time td from time t3, when the gate voltage G falls to the same voltage level as the power supply voltage Vcc, the output voltage Vo begins to fall. At time t5, when the output voltage Vo becomes lower than the power supply voltage Vcc by a threshold voltage “h” of the NMOS transistor 138, the NMOS transistor 138 is brought to an on state. Thereby, the NMOS transistor 137 is brought to an off state. That is, the gate charge of the output transistor 132 is no longer discharged via the NMOS transistor 137. On the other hand, the slow discharge through the NMOS transistor 139 is continued. At time t6, when the discharge is completed and the gate voltage G is set to a low level, the output voltage Vo also becomes a low level. When a load (not shown) coupled to the output terminal To is a resistive device, an output current Io exhibits the same change as the output voltage Vo, as illustrated in FIG. 8.
In this way, in switching the output transistor 132 from an on state to an off state, when the output voltage Vo is as high as the power supply voltage Vcc, the NMOS transistor 137 is brought to an on state. Accordingly, the gate charge of the output transistor 132 is discharged at high speed. After that, when the output voltage Vo becomes lower than the power supply voltage Vcc by the threshold voltage of the NMOS transistor 138, the NMOS transistor 137 is brought to an off state. Accordingly, the gate charge of the output transistor 132 is no longer discharged at high speed.
On the other hand, in switching the output transistor 132 from an on state to an off state, the NMOS transistor 139 is brought to an on state by the control signal “a” at a low level. Accordingly, the gate charge of the output transistor 132 continues being discharged via the current limiting element 140 and the transistor 139, more slowly than via the NMOS transistor 137.
That is, it is possible for the power supply control circuit 100 to shorten time (delay time td) after starting the turn-off operation (time t3) until the output voltage Vo starts changing (time t4), by performing discharge operation using the two discharge paths as described above. That is, the turn-off time (from time t3 to time t6) can be shortened. At the same time, it is possible for the power supply control circuit 100 to make slow a slew rate of the output voltage Vo in the turn-off operation.